Non-volatile random-access memory (NVRAM) is a type of random-access memory (RAM) that retains its information when power is turned off (non-volatile). This is in contrast to DRAM or SRAM which maintain data as long as power is applied.
Since decades, computers load instructions and data from a non-volatile memory (NVM), typically a Flash drive, which is slow but has big storage capacity. They are loaded into RAM, which has small storage capacity because it is not dense. The processor can then execute the instructions, allowing to read data, compute new one, and to save them back to NVM.
But what if RAM was persistent and dense and, why not, as fast as SRAM ? What would the architecture of the processor look like ? The notion of file would it still be useful ? In what form ? How to manage a computer which has no need to save data ? Which impact on performances ?
Lots of researchers are working to design a NVRAM that would be dense, cheap, fast to write, fast to read, consume low power, has a great endurance. Many technologies are being investigated to obtain different compromises between these qualities. The graal, a type of memory that would have all of them, is usually referred to as universal memory.
Recently, some NVRAM technologies have become mature enough to build prototypes and the impact on computer science can start to be investigated. In the following, I give some information on the hardware (including manufacturers and technologies), then I briefly give some computer science topics that are impacted by the existence of NVRAM.
Lots of manufacturers are working on the design of NVRAM around the world : Toshiba, Panasonic, Fujitsu, Samsung, Everspin, Ramtron, Micron, SanDisk, Lapis, Qualcomm, Infineon, Adesto Technologies, Avalanche Technology, Cypress, Spin Transfer Technology, IMEC, Crocus technology.
In France, ST MicroElectronics and Spintec are industrials investigating in this area. On the academic part, the CEA Leti and the LIRMM are working on various NVRAM technologies.
For more details on the technologies and the trends, you can read :
The Tuna http://opennvram.org/ board allows to emulate various access latencies thanks to an FPGA design between the ARM Cortex A9 and the DDR3.
This is not really NVRAM (not dense, requires electrical power):
Various scientific topics are impacted by the existence of NVRAM. I try to sort them in the following. Also, some position papers give an overview of the impact of NVRAM on computer science :
Authors propose 3 ways of replacing L2/L3 caches by STT, but no experimental validation.
Lots of work change the processor architecture. Basically, the goal is to replace parts of the memory hierarchy, e.g. cache, with NVRAM, and simulate the gains (performances, energy etc.). I am not exhaustive here.
If you want to read only one article in this category, read this one: [Mittal et al., 2015].
Some works concern the replacement of Hard/Flash drives for mass storage :
If the working memory contains NVRAM, data can be made persistent without the use of a File System API, achieving orthogonal or transparent persistency.
Persistence is said to be ”orthogonal” or ”transparent” when it is implemented as an intrinsic property of the execution environment of a program. An orthogonal persistence environment does not require any specific actions by programs running in it to retrieve or save their state.
Orthogonal persistence can be achieved by the use of a persistent heap. In this case, applications use a transactional API to allocate, deallocate, and modify persistent objects. On recovery, the application retrieves a special “root” object from which it can reach the others:
and proposes an API to allocate in NVRAM (see table 1).
An hypothesis made is that NVRAM accesses are slower than in DRAM (therefore: DRAM is used as a cache).
Evaluation: their work, they ask 250GB to mmap() on which they mount a PMFS file system thanks to the PMEP emulation platform.
Other works achieve orthogonal persistence without requiring programmers to use a dedicated API:
Lots of works investigate the use of PCM+DRAM in order to benefit from the density of PCM and save energy. A key concern of these works is to increase the endurance of PCM, using various wear-levelling techniques:
Other works deal with other types of memory, typically MRAM, removing the need for wear-levelling:
What kind of optimizations can we expect from the introduction of NVRAM in peripherals themselves ? I have found no work on that but some ideas I want to investigate, with other researchers (thanks O. Sentieys) include:
As few hardware is available yet, it is difficult for computer scientists to setup systems dedicated to NVRAM and evaluate their performances. Although the realism of the simulation may be a real issue, the benefits of emulation are numerous:
Simulating NVRAM is an active scientific topic. Some tools already exist; I briefly detail them in the following.
Another approach is to extrapolate from the results with DRAM. A great article demonstrate the limits of this approach:
The advantage of circuit-level simulators is that they are potentially very precise. The problem is to connect them to whole-system emulators (with memory management, cache system, etc.).
[Ait Aoudia et al., 2014] Ait Aoudia, F., Marquet, K., and Salagnac, G. (2014). Incremental checkpointing of program state to nvram for transiently-powered systems. In ReCoSoC - 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France.
[Bailey et al., 2011] Bailey, K., Ceze, L., Gribble, S. D., and Levy, H. M. (2011). Operating system implications of fast, cheap, non-volatile memory. In 13th Workshop on Hot Topics in Operating Systems, HotOS XIII, Napa, California, USA, May 9-11, 2011. USENIX Association.
[Cargnini et al., 2014] Cargnini, L. V., Torres, L., Brum, R. M., Senni, S., and Sassatelli, G. (2014). Embedded memory hierarchy exploration based on magnetic random access memory. Journal of Low Power Electronics and Applications, 4(3):214–230.
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[Caulfield et al., 2010b] Caulfield, A. M., De, A., Coburn, J., Mollow, T. I., Gupta, R. K., and Swanson, S. (2010b). Moneta: A high-performance storage array architecture for next-generation, non-volatile memories. In Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO ’43, pages 385–395, Washington, DC, USA. IEEE Computer Society.
[Chakrabarti et al., 2014] Chakrabarti, D. R., Boehm, H.-J., and Bhandari, K. (2014). Atlas: Leveraging locks for non-volatile memory consistency. In Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications, OOPSLA ’14, pages 433–452, New York, NY, USA. ACM.
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